multi source error using Xilinx

[rhajj]

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Code VHDL - [expand]
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
 
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
 
entity Encoder_eight is
    Port ( message : in  STD_LOGIC_VECTOR (7 downto 0);
           clk : in  STD_LOGIC;
           codeword : out  STD_LOGIC_VECTOR (11 downto 0));
end Encoder_eight;
 
architecture Behavioral of Encoder_eight is
 
 
 
component summation is 
    port ( p1_out : in std_logic_vector ( 11 downto 0);
             p2_out : in std_logic_vector ( 11 downto 0);
             p3_out : in std_logic_vector ( 11 downto 0);
             p4_out : in std_logic_vector ( 11 downto 0);
--           CLK    : in std_logic;
             p1_sum : out std_logic;
             p2_sum : out std_logic;
             p3_sum : out std_logic;
             p4_sum : out std_logic
          );
end component;
 
component Append is 
    port ( message: in std_logic_vector ( 7 downto 0);
             p1_sum : in std_logic;
             p2_sum : in std_logic;
             p3_sum : in std_logic;
             p4_sum : in std_logic;
             codeword:out std_logic_vector ( 11 downto 0)
          );
end component;
 
 
signal p1_out , p2_out , p3_out , p4_out:  std_logic_vector (11 downto 0):=(others =>'0');
signal p1_sum , p2_sum , p3_sum , p4_sum : std_logic;
signal tmp , tmp1 , tmp2 , tmp3 : std_logic := '0';
 
 
 
begin
 
L2 : summation port map ( p1_out , p2_out , p3_out , p4_out , p1_sum , p2_sum , p3_sum , p4_sum);
L3 : Append port map ( message, p1_sum , p2_sum, p3_sum , p4_sum  , codeword );   
 
 
   p1_out <= "010101010101";
   p2_out <= "001100110011";
   p3_out <= "000011110000"; 
    p4_out <= "000000001111"; 
    
process ( p1_out , p2_out , p3_out , p4_out) 
begin 
 
 
-- for the adddition of the vectors 
 
        tmp  <= p1_out(0) XOR p1_out(1) XOR p1_out(2) XOR p1_out(3) XOR p1_out(4) XOR p1_out(5) XOR p1_out(6) XOR p1_out(7) XOR p1_out(8) XOR p1_out(9) XOR    p1_out(10) XOR p1_out(11);
        tmp1 <= p2_out(0) XOR p2_out(1) XOR p2_out(2) XOR p2_out(3) XOR p2_out(4) XOR p2_out(5) XOR p2_out(6) XOR p2_out(7) XOR p2_out(8) XOR p2_out(9) XOR p2_out(10) XOR p2_out(11);
        tmp2 <= p3_out(0) XOR p3_out(1) XOR p3_out(2) XOR p3_out(3) XOR p3_out(4) XOR p3_out(5) XOR p3_out(6) XOR p3_out(7) XOR p3_out(8) XOR p3_out(9) XOR p3_out(10) XOR p3_out(11);
        tmp3 <= p4_out(0) XOR p4_out(1) XOR p4_out(2) XOR p4_out(3) XOR p4_out(4) XOR p4_out(5) XOR p4_out(6) XOR p4_out(7) XOR p4_out(8) XOR p4_out(9) XOR p4_out(10) XOR p4_out(11);
        
 
    
    p1_sum <= tmp;
    p2_sum <= tmp1;
    p3_sum <= tmp2;
    p4_sum <= tmp3;
 
end process;
    codeword(0) <= p1_sum;
    codeword(1) <= p2_sum;
    codeword(2) <= message(0);
    codeword(3) <= p3_sum;
    codeword(4) <= message(1);
    codeword(5) <= message(2);
    codeword(6) <= message(3);
    codeword(7) <= p4_sum;
    codeword(8) <= message(4);
    codeword(9) <= message(5);
    codeword(10) <= message(6);
    codeword(11) <= message(7); 
 
 
end Behavioral;

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this is giving me the following error :
please help

ERROR:Xst:528 - Multi-source in Unit <Encoder_eight> on signal <p2_sum>
ERROR:Xst:528 - Multi-source in Unit <Encoder_eight> on signal <p3_sum>
ERROR:Xst:528 - Multi-source in Unit <Encoder_eight> on signal <p4_sum>
ERROR:Xst:528 - Multi-source in Unit <Encoder_eight> on signal <p1_sum>

 

[Tetik]

Your component summation has outputs pX_sum connected to signals pX_sum. Later, you are assigning the signals pX_sum with signals tempX. So, both the component's output and the nets tempX drive the signals pX_sum. Each signal must have an unique source.

 

[rhajj]

okay so can u suggest the way to fix it ? should i rename or something ? i'm new at this

 

[rhajj]

i tried removing the tmp signal but instead it still gave me multisource in codeword<0> , codeword<1>, codeword<3>, codeword<7>

 

[TrickyDicky]

Codeword is also the output from the append component.
You need to think like circuit boards - if components are chips, the signals are wires. In this case, you connected 2 wires together.

 

[FvM]

Removing a tmp signal can't resolve the issue. You need to reconsider the circuit. The p1_sum etc. signals can be only driven by one side, either as output of the summation block or in the process.

 

[wtr]

Just a side note..........if you do have multiple sources...you need to make sure only one is connected at any particular time. This is achieved through a mux