multicycle risc processor
Well as u correctly guessed it I am designing a Analog Devices ADSP 21020 processor IP core. I have a 40 bit data bus which I have to connect to an external memory like SRAM,the SRAM I am using because the controller is easier to manage. :| I have to either use 5 SRAMs for data transfer or use a single SRAM and do some sort of interfacing so that I can read 5 bytes in subsequent cycles.
Architecture I have to follow strictly according to the manual,in case you cant find on the net plz let me knw. And what exactly do u mean by instruction pipeline and parsing...please clarify a bit,I am not very proficient in architectural designs. My ALU part is more or less up and running, I have a fixed point ALU,floating point unit,shifter and multipliers. Also a 10 port register file which was really cumbersome and have to take care of lots of setup and hold violations. Now the main stumbling block is the Controller FSM design, I have seen a couple of standard designs like XSOC,RISC8,OpenRISC etc found on the net,but none of them have multicycle implementations and most of them use on chip block RAM as source of instructions and data.
Also I am a real newbie at designing large systems on my own, so I am finding myself devoid of engineer's toolkit so to say. :idea: Really need some serious help here