sixdegrees
Junior Member level 2
multicycling instructions
Hello,
I am designing a multicycle RISC CPU which has lots of instructions and various functional units. Now these instructions take variable number of clock cycles and I am required to build the controller FSM for these. I have completed all the ALU functions like fixed point operations,floating point operations,shifter,multiplier etc and I also have the 10 port register file up and ready.But I am required to code the Controller state machine and am struck. From the various examples I got from Opencores etc, all use a simple 1 cycle simplistic alu which returns data on the next cycle but nowhere I can find any info about multicycle controller. I am using Verilog and dont understand VHDL so all you geniuses plz suggest something in Verilog on how to go about it.
I have another big problem,I am required to read my instructions and data from external SRAM chips and have a 40 bit data and 48 program memory bus,so in case I want to connect my FPGA to external RAM chips I will have to use 8 8KSRAM chips which have a 8 bit data bus which sounds really clumsy and unscientific. Can some1 suggest anything?
Added after 3 hours 2 minutes:
Seems like nobody has worked with multi cycle CPU implementations!!
Guess I will have to search somewhere else....I tried reading some organisation books like Patterson and Hennesy but couldnt think of a way to actually map it down to Verilog
Hello,
I am designing a multicycle RISC CPU which has lots of instructions and various functional units. Now these instructions take variable number of clock cycles and I am required to build the controller FSM for these. I have completed all the ALU functions like fixed point operations,floating point operations,shifter,multiplier etc and I also have the 10 port register file up and ready.But I am required to code the Controller state machine and am struck. From the various examples I got from Opencores etc, all use a simple 1 cycle simplistic alu which returns data on the next cycle but nowhere I can find any info about multicycle controller. I am using Verilog and dont understand VHDL so all you geniuses plz suggest something in Verilog on how to go about it.
I have another big problem,I am required to read my instructions and data from external SRAM chips and have a 40 bit data and 48 program memory bus,so in case I want to connect my FPGA to external RAM chips I will have to use 8 8KSRAM chips which have a 8 bit data bus which sounds really clumsy and unscientific. Can some1 suggest anything?
Added after 3 hours 2 minutes:
Seems like nobody has worked with multi cycle CPU implementations!!
Guess I will have to search somewhere else....I tried reading some organisation books like Patterson and Hennesy but couldnt think of a way to actually map it down to Verilog