Multi-cycle and false path

[srpatel9]

false path

Hi all,

I am new to enounter RC. I do not understand Multi-cycle and false path commands. Its would be great if someone could take out some time and explain me these commands.

Thanks
Saurabh

 

[ljxpjpjljx]

efficient identification of multicycle false path

multi-cycle path is the path which need to use more than one cycle to transfer data. false path is cross-clock domain path which don't need to check!

 

[ssj]

false path definition

any path for which data is not sampled in one clock cycle ( default ) is a multicycle path.
eg : if enable of flop is asserted after every two cycle, any path ending at the flop is a multicycle of three.

false paths are the ones which would never be sensitized while chip is functional.

eg: enable of flop is tied to zero

 

[srpatel9]

false path for synchronous clocks

Hi all,

Can you guys give some more examples of multi-path and false path. Still this concept is hazy in my mind.

How do you synthesize circuits have a generated clock (like a asynchronous circuit )in encounter RC?

THanks guys

 

[lakshman.ar]

define multi-cycle instruction

How do you synthesize circuits have a generated clock (like a asynchronous circuit )in encounter RC?

sol : the constraint file which is provided during synthesis, must contain the "create generated clock" constraint !

IMHO, generated clock comes into picture only in case of synchronous clock domains ..... how can generated clock play a role in asynchronous designs ???

 

[srpatel9]

examples of false paths

Hi,

I have a self-timed circuit. It is not a completely synchronous design - you can say it is puesdo-synchronous.

Circuit Description:

There are two level in the circuit. The first level works on global clock. The output of the 1st level goes to a CMOS logic that generates clock for the 2nd level.

Now I want to define constraints for the 2nd level wrt to this generated clock.

Currently the 2nd level is unconstrainted. It fails to recognize the generated clock as clock of the 2nd level.

I donot know how to define it as clock so that constraints can be set and I can optimize the ckt.

I am using encounter RC.

I did some digging in this matter and came to know that a command in DC -generated clock that can do the job. I can be wrong.

Since i am new with RC, I was wondering is there a way to use DC commands in RC.

Any kind of help is appreciated.

Thanks in advance.

 

[jayTudu]

zero cycle path define

Hi ,

You can refere the paper Titled: "Efficient Identification of Multicycle False Path" Author: K Yang, K Chen,
Publisher: IEEE
The paper clearly gives the definition of both the concepts u r loking for.
Carry on,
Jay