multi clock constrain

[quiet83]

Now in my design, there are serveral clock signals generated by one clock.
Is there any method that can keep all the generated clock signals edge aligned?
Because the load of those clock signals are not the same, the edges of those clock signals are not aligned.
Is it possible to do it in the synthesis or back-end?
Thanks.

 

[ads_ee]

you'll have to balance the loads on the clock trees that you've produced. Not sure about how to get the tools to do this, I haven't been involved in ASIC design for 8+ years.