I'm designing a simple circuit using Multi Supply Voltage. I'm using synopsys Dc Compiler for synthesys, therefore I must use UPF.
For the physical implementation I will use Cadence encounter which doesn't support UPF, but requires a CPF.
Since my design is simple (I have only one power mode) the translation from UPF to CPF is simple, but is it safely using UPF in synthesis and CPF in P&R ? Is this approach standard or coud rise some issues?
many companies use mix of tools so it should be fine to use two tools. Of course there will be issues because you will have to "convert" UPF to CPF for cadence. Any kind of conversion is prone to user errors which have to properly QA'ed.
There is nothing new about companies using a mix of the tools and flows which adds more qualification time but that is part of industry so that people are not dependent on single EDA provider and chose the tool which performs the best.
in the above case many companies use DC for front end synthesis followed by encounter for the P&R