The datasheets I've seen usually say that if you write to both ports of a dual port RAM at the same address the results are indeterminate not one port having priority over the other, or they never even mention what results to expect. Only in cases where the clocks to the dual port are skewed enough that the write setup/holds don't interfere with each other allowing both writes to complete correctly, which means the second one wins (though the OP specified a single clock, clk).
I'm think that there may be confusion over the fact that writing and reading the same address usually favors the read or the write or the priority may be programmable like Xilinx's: read before write, write before read, and no change options.