[MOVED] verilog code for 3-bit synchronous counter

[pavani vanka]

please send me the code for 3-bit synchronous counter in verilog hdl. please its urgent

 

[sv1437]

Re: verilog code for 3-bit synchronous counter

Here is the code:

---

Code Verilog - [expand]
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module synccounter(clk,reset,out);
input clk,reset;
output [2:0] out;
 
reg [2:0] out;
 
always @(posedge clk)
begin
 if (reset == 1'b1)
   out <= 3'b000;
    else
     out <= out+1'b1;
 
end
 
endmodule

---

 

[jhunjhun]

Re: verilog code for 3-bit synchronous counter

this program gives output only 001.
how it works as counter?