[Moved] variable data type verilog HDL

[preethi19]

it is put that variable data types can be assigned only inside a procedure, task or function. check the following verilog code

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Code Verilog - [expand]
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module mult_acc 
(
input [7:0] ina,inb;
input clk, aclr;
ouput [15:0] out;
)
wire [15:0] mult_out, adder_out;
reg [15:0] out;
 
assign adder_out=mult_out+out;
always @ (posedge clk or posedge aclr)
                if (aclr) out=16'h0000;
                else out=adder_out;
 
multa u1(.in_a(ina), .in_b(inb), .m_out(mult_out));
 
endmodule

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just took this example from the net. I'm just starting with the basics so i don't know much abt the entire code but my doubt here is reg is a variable data type right and it should be within a procedure which in this case should be inside always block but why is it not der. can someone pls explain me why reg is used outside and if we can use variable data types outside in wat cases do we use it (i mean to describe wat)

 

[kommu4946]

it is put that variable data types can be assigned only inside a procedure, task or function

With above statement i conclude that you have confusion about vhdl and verilog.First of all there are no procedures in verilog only procedural blocks initial,always blocks (vhdl has procedures).Similarly in vhdl there are no tasks (vhdl has functions and procedures)..for verilog you can not declare variables inside procedural blocks ,initial and always.You can declare them inside functions and tasks.