I am designing my D flip flop for SAR control logic circuit in 180nm Technology in 1volt power supply. I am attaching the link for the SAR LOGIC Below (PAGE NO.:5 figure 1) ipnpr.jpl.nasa.gov/progress_report2/XIII/XIIIW.PDF.
I believe the load is less than 100femto.
my design for D flip flop is given above.
right now i m designing the circuit for current starving mode.
when i am calculating the average power their are spikes during switching which is causing rise in power.Spikes are in ampere range
Kindly help me reduce the power of the involved D Flip flop. Any weblink or papers/thesis are welcome.