[moved] ultra low power D flip flop

[pankaj jha]

Hi all
I m designing a transmission gate based D flip flop with set and reset
link for design is given below
www.nxp.com/documents/data_sheet/74LVC2G74.pdf


the key issue is im not able to reduce power below nanowatt range.
any help to make this design in picowatt range will be welcomed
thank you

 

[erikl]

You should reveal more info, I think:

• leakage or switching power?
• which process?
• which supply voltage?
• which load?

 

[pankaj jha]

You should reveal more info, I think:

• leakage or switching power?
• which process?
• which supply voltage?
• which load?

Hi

I am designing my D flip flop for SAR control logic circuit in 180nm Technology in 1volt power supply. I am attaching the link for the SAR LOGIC Below (PAGE NO.:5 figure 1)
ipnpr.jpl.nasa.gov/progress_report2/XIII/XIIIW.PDF.

I believe the load is less than 100femto.
my design for D flip flop is given above.
right now i m designing the circuit for current starving mode.

when i am calculating the average power their are spikes during switching which is causing rise in power.Spikes are in ampere range

Kindly help me reduce the power of the involved D Flip flop. Any weblink or papers/thesis are welcome.

 

[erikl]

... right now i m designing the circuit for current starving mode.

I guess this won't help a lot against the switching spikes.

... their are spikes during switching which is causing rise in power.Spikes are in ampere range

Try to use MOSFETs with larger Vth values - if your process offer such. Otherwise reduce the power supply voltage - at least for the FFs.