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[Moved]: regarding design for testability

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swapna julakanti

Newbie level 4
Aug 27, 2015
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please help me in design for testability
any free online course or notes please share
thanks in advance

Re: regarding design for testability

iam new to course.subject name is design for testability
now the topic going is fault simualtion,scan test,scoap etc

Re: regarding design for testability

What test you are going to carry out? Is it analog Test or Digital tests?

If it is analog Tests Do you mean ESD latch up like that?

Can you please more specific on these?

Re: regarding design for testability

digital test kenambo
mainly scan design iam feeling tough which include muxed d scan cell,lssd,clocked scan,dft architectures like full ,partial and random scan

Re: regarding design for testability


check this PDF

If you are using Encounter RTL compiler you can find a detailed document of DFT (which include the scan chain and everything) in Cadence documentation.

Do you write RTL code? or you are checking RTL code with RTL compiler?

I hope you are testing. so better you study the cadence Encounter RTL compiler document It will be enough.

And check this PDF also.. I think this is what you need...

If you need more information, share the specific thing you need.

Re: regarding design for testability

Read this book:
Testing of Digital Systems
N. K. Jha, Princeton University, New Jersey
S. Gupta, University of Southern California
Re: regarding design for testability

DFT should not add more than 1~10 % of the product cost depending on volume.

It should detection >99% of most common faults, which are related to manufacturing and design flaws. Advanced test design will also location >99% of faults.

There is a wide array of tools from BITE, (built-in Test equip), Analog, Digital, ATE low level and functional testers ($K xxx) POST, Auto-cal.

The most important aspect is for an experienced Test Engineer to be part of the design team from the start and ensure the design spec is detailed enough to use a starting point for Test verification.

Much of Design , in DFT is electro-mechanical as layout, chip, PCB and system interconnects are critical for access to test points. But there is also a lot of parametric tests and statistics involved with monitoring Quality with test results.

Xbar, 3 sigma and Design Margin Analysis and testing (Cpk) during DVT with all environmental stress tests incl HALT, that determine which subset of tests will be kept for production. HASS is another method for accelerating test margin to predict failures.
Re: regarding design for testability

Most important is the Test Engineer is included in the design phse to ensure good specs ensure Prod Eng writes good specs to test . and doesn't become an afterthought.

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