Jan 9, 2016 #1 S Sunayana Chakradhar Member level 5 Joined Oct 24, 2014 Messages 85 Helped 2 Reputation 4 Reaction score 2 Trophy points 8 Activity points 742 Hello, I am currently doing a pre RTL pin planning for my Zynq 7020 FPGA. I have a very basic question. I have few interfaces on the PS and the AXI EMC v3.0 ip core on the PL EMIO. Can i do the pin planning for this IP core before synthesizing itself?
Hello, I am currently doing a pre RTL pin planning for my Zynq 7020 FPGA. I have a very basic question. I have few interfaces on the PS and the AXI EMC v3.0 ip core on the PL EMIO. Can i do the pin planning for this IP core before synthesizing itself?