electronhole
Junior Member level 1
Hi, I need to design a differential Low-Noise Amplifier (LNA) using the IBM 90nm CMOS process with f0= 2.3 to 2.6GHz, Differential Rin= 100Ω; S11 < -15dB, Voltage gain ≥20 dB, NF ≤2dB, IIP3 ≥-5dBm.
can any one help how to proceed with the design meeting all the contrains with minimum power.
can any one help how to proceed with the design meeting all the contrains with minimum power.