asdf44
Advanced Member level 4
What's the conventional wisdom on this these days?
Of course I know there are no internal Z's, instead I want the tools to infer a mux.
Specifically I'd like to implement a large register file by sending around a shared memory bus and hanging 100 or so modules off it that each implement one register. The models will 'Z' the shared data_out bus when their address isn't selected.
From a code point of view it's compact and flexible - I'll have different modules for read-only, read/write, latches with clear functionality etc and new registers can be plugged in or removed with the bare minimum of modifications.
Although I've used this on a small scale in Xilinx ISE I've shied away from it on past major designs citing the general wisdom that tri-states are to be avoided. But I'd like to re-evaluate that for an upcoming design.
EDIT: Sorry, meant to put in FPGA section.
Of course I know there are no internal Z's, instead I want the tools to infer a mux.
Specifically I'd like to implement a large register file by sending around a shared memory bus and hanging 100 or so modules off it that each implement one register. The models will 'Z' the shared data_out bus when their address isn't selected.
From a code point of view it's compact and flexible - I'll have different modules for read-only, read/write, latches with clear functionality etc and new registers can be plugged in or removed with the bare minimum of modifications.
Although I've used this on a small scale in Xilinx ISE I've shied away from it on past major designs citing the general wisdom that tri-states are to be avoided. But I'd like to re-evaluate that for an upcoming design.
EDIT: Sorry, meant to put in FPGA section.
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