[Moved]: Insertion Delay in CTS

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vaibhavgahlot

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Why insertion delay minimization is one of the CTS goal? How does insertion delay affects setup and holdtime?
 

The minimation is goal because:
1. The longer clock delay, the higher possibility of more buffer cells --> the higher of power consumption, and the area.
2. The longer clock path delay, there are more negative effect from crosstalk and on-chip-variation ( OCV ) factors.

Please find then Slack calculation formluar for setup and hold with including launch and capture clock delays.
You then can find out how was the effection of clock delay.
 

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