[Moved]Implementing 1.8V output voltage in 0.18um process?

[twteng]

Hi All:
Can anybody answer my query, I am going to design two version of LDO:
1. 1.8V output in 0.18um 1.8V process
2. 3.3V output in 0.18um 3.3V process(using OD2 layer)
the dropout voltage is 200mV
Can I plug in 2V(1.8+dropout) or 3.5V(3.3+dropout) voltage in the input of LDO?
your help would be appreciate, thanks a lot.

 

[erikl]

Can I plug in 2V(1.8+dropout) or 3.5V(3.3+dropout) voltage in the input of LDO?

Sure. If you want the same circuit for both I/O voltages, use 5V (≧ 3.5V) -tolerant transistors.

 

[leo_o2]

If you want good performance like PSRR, regulation, it is better to have more headroom for LDO.
If VIN=VO+drop-out, it means no margin.

 

[twteng]

Hi erikl:
I don't quite get your point? could you clarify more? thanks

Hi leo_o2:
You means to enlarge the drop-out voltage or VIN? could you explain more details.
To extend this question, what region should pass transistor(PMOS) operate?
as i knew, in sat. region--> good psrr and regulation performance,
in linear region--> save power.
Am I right?

expecting you both reply, thanks a lot.

 

[leo_o2]

Yes.
In drop-out region, psrr will drop to 0.
Usually, psrr will be max for VIN>=VO+1V.