Yes rightHi,
so you basically want to generate 26,000,500 Hz?
Klaus
The 26MHz frequency is freely available on chip. Actually it is the reference frequency for an all digital phase lock loop (ADPLL). As the TDC is built around the ADPLL, off-chip solutions like the programmable PLL you mentioned do not work here. We want the solution to be made on-chip and also area efficient.Hi,
I wonder why you wrote "from a single 26MHz crystal oscillator".
...especially since accuracy is not the problem.
I´d use a programmable PLL chip. Like CDCE913. Then you are rather flexible.
Or even more flexible with the 2-PLL type CDCE925. Then you may program both output frequencies.
Klaus
Oh I am sorry. Can you please move the thread to the IC design section? I can't do it myself.Hi,
so yo are talking about chip design?
(You are positing in the "Analog Circuit Design" section = not IC design)
Klaus
Basically I need to fill in a lookup table by repeatedly feeding time increments to the inputs of the TDC. The TDC has two inputs, namely Start and Stop. The difference between the two is to be resolved by the TDC. So for every cycle (1/26MHz) the time difference is incremented by 1 time step, where each time step is 0.7ps which is made by two 26MHz clocks where the second is further offset by 500Hz.Hi,
when I understand the requirements correctly, then it should be internal. So no external AD9958.
And further I think a DDS, especially when driven by an NCO is also not the way to go, because the task is to get linear phase shift with respect to each other. While an NCO causes steps.
.. at least this is how I understand the requirement.
Klaus
The 9958 is not to use as a device, rather an approach to his IC design, theHi,
when I understand the requirements correctly, then it should be internal. So no external AD9958.
And further I think a DDS, especially when driven by an NCO is also not the way to go, because the task is to get linear phase shift with respect to each other. While an NCO causes steps.
.. at least this is how I understand the requirement.
Klaus
this are the calculated by (1/26000000) - (1/26000500)where each time step is 0.7ps
For AD9958 the frequency tuning resolution is claimed to be 0.12Hz. What it means is that I can have minimum 499.88Hz and maximum 500.12Hz as the offset frequency which far exceeds my design requirements. I can trade off lower resolution versus power or area as far as my design specs are concerned. But yet I am not sure whether it is the only way to go. I'm waiting for other less simpler alternatives if there are any.Hi
this are the calculated by (1/26000000) - (1/26000500)
Makes sense.
So this can´t be fulfilled with an NCO. An NCO output step size will be 1/26000000 s
(Didn´t check whether the AD9958 uses an NCO at all)
So from my understanding you definitely need a low noise VCO feedbacked as a PLL.
Klaus
Just want to add:
I meant low phase noise / phase jitter. The problem is that two frequency oscillators somehow will influence each other. Expect non ideal linear phase shift, but some distortions.
That does not seem to be a good solution. We are going to use TDC as part of an all digital PLL. We want to avoid analog PLLs. Using analog approaches in a completely digital design is not recommended at all.So from my understanding you definitely need a low noise VCO feedbacked as a PLL.
It depends. What are you going to do with the dividers?Do you have room for two big, dumb frequency dividers?
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