[moved] Generate two signal tones with a frequency offset (on-chip)

[dirac16]

How to generate two frequency tones with a 500Hz frequency offset from a single 26MHz crystal oscillator? Because that is part of an integrated circuit we cannot use signal generators and so only have to make these on chip. Any ideas?

 

[KlausST]

Hi,

the task is not clear.

Sine wave or square wave?
How do you want to do the input? with a pot, keyboard...

What accuracy do the 500Hz need?

What is the frequency range of the initial output frequency.

Klaus

 

[dirac16]

The input frequency is a 26MHz square-wave with 50% duty cycle. The frequency offset need not be that accurate, actually a +-20-30% error is fine.

We want the signals for on-chip calibrating a time to digital converter (TDC) with a time ramp input. Also with a frequency offset of 500Hz we get a 0.74ps/cycle input ramp step, which is quite sufficient for our purpose.

 

[KlausST]

Hi,

so you basically want to generate 26,000,500 Hz?

Klaus

 

[dirac16]

Hi,

so you basically want to generate 26,000,500 Hz?

Klaus

Yes right

 

[KlausST]

Hi,

I wonder why you wrote "from a single 26MHz crystal oscillator".
...especially since accuracy is not the problem.

I´d use a programmable PLL chip. Like CDCE913. Then you are rather flexible.

Or even more flexible with the 2-PLL type CDCE925. Then you may program both output frequencies.

Klaus

 

[dirac16]

Hi,

I wonder why you wrote "from a single 26MHz crystal oscillator".
...especially since accuracy is not the problem.

I´d use a programmable PLL chip. Like CDCE913. Then you are rather flexible.

Or even more flexible with the 2-PLL type CDCE925. Then you may program both output frequencies.

Klaus

The 26MHz frequency is freely available on chip. Actually it is the reference frequency for an all digital phase lock loop (ADPLL). As the TDC is built around the ADPLL, off-chip solutions like the programmable PLL you mentioned do not work here. We want the solution to be made on-chip and also area efficient.

 

[KlausST]

Hi,

so yo are talking about chip design?
(You are positing in the "Analog Circuit Design" section = not IC design)

I´m not familiar with IC design. But I think it´s a good idea to tell which parts with what features you use.

Klaus

 

[dirac16]

Hi,

so yo are talking about chip design?
(You are positing in the "Analog Circuit Design" section = not IC design)

Klaus

Oh I am sorry. Can you please move the thread to the IC design section? I can't do it myself.

 

[danadakk]

Design a dual DDS approach ?

Like this - https://www.analog.com/en/products/ad9958.html


Regards, Dana.

 

[KlausST]

Hi,

when I understand the requirements correctly, then it should be internal. So no external AD9958.

And further I think a DDS, especially when driven by an NCO is also not the way to go, because the task is to get linear phase shift with respect to each other. While an NCO causes steps.

.. at least this is how I understand the requirement.

Klaus

 

[dirac16]

Hi,

when I understand the requirements correctly, then it should be internal. So no external AD9958.

And further I think a DDS, especially when driven by an NCO is also not the way to go, because the task is to get linear phase shift with respect to each other. While an NCO causes steps.

.. at least this is how I understand the requirement.

Klaus

Basically I need to fill in a lookup table by repeatedly feeding time increments to the inputs of the TDC. The TDC has two inputs, namely Start and Stop. The difference between the two is to be resolved by the TDC. So for every cycle (1/26MHz) the time difference is incremented by 1 time step, where each time step is 0.7ps which is made by two 26MHz clocks where the second is further offset by 500Hz.

 

[danadakk]

Hi,

when I understand the requirements correctly, then it should be internal. So no external AD9958.

And further I think a DDS, especially when driven by an NCO is also not the way to go, because the task is to get linear phase shift with respect to each other. While an NCO causes steps.

.. at least this is how I understand the requirement.

Klaus

The 9958 is not to use as a device, rather an approach to his IC design, the
general concept of DDS based signal generation.

DDS phase control is 14 bit res, in the 9958, he of course can choose whatever target
he wants, and they are linear phase "sweepable" as shown by datasheet.

The AD9958 can perform up to a 16-level modulation of frequency, phase, or amplitude (FSK, PSK, ASK). Modulation is performed by applying data to the profile pins. In addition, the AD9958 also supports linear sweep of frequency, phase, or amplitude for applications such as radar and instrumentation.​

But again, thats this device, since he is designing silicon from scratch he can do
whatever he wants, within process and architecture constraints.

Regards, Dana.

 

[KlausST]

Hi

where each time step is 0.7ps

this are the calculated by (1/26000000) - (1/26000500)
Makes sense.

So this can´t be fulfilled with an NCO. An NCO output step size will be 1/26000000 s
(Didn´t check whether the AD9958 uses an NCO at all)

So from my understanding you definitely need a low noise VCO feedbacked as a PLL.

Klaus

Just want to add:
I meant low phase noise / phase jitter. The problem is that two frequency oscillators somehow will influence each other. Expect non ideal linear phase shift, but some distortions.

 

[dirac16]

Hi

this are the calculated by (1/26000000) - (1/26000500)
Makes sense.

So this can´t be fulfilled with an NCO. An NCO output step size will be 1/26000000 s
(Didn´t check whether the AD9958 uses an NCO at all)

So from my understanding you definitely need a low noise VCO feedbacked as a PLL.

Klaus

Just want to add:
I meant low phase noise / phase jitter. The problem is that two frequency oscillators somehow will influence each other. Expect non ideal linear phase shift, but some distortions.

For AD9958 the frequency tuning resolution is claimed to be 0.12Hz. What it means is that I can have minimum 499.88Hz and maximum 500.12Hz as the offset frequency which far exceeds my design requirements. I can trade off lower resolution versus power or area as far as my design specs are concerned. But yet I am not sure whether it is the only way to go. I'm waiting for other less simpler alternatives if there are any.

--- Updated Oct 21, 2021 ---

So from my understanding you definitely need a low noise VCO feedbacked as a PLL.

That does not seem to be a good solution. We are going to use TDC as part of an all digital PLL. We want to avoid analog PLLs. Using analog approaches in a completely digital design is not recommended at all.

 

[JWHassler]

Do you have room for two big, dumb frequency dividers?

 

[dirac16]

Do you have room for two big, dumb frequency dividers?

It depends. What are you going to do with the dividers?