Hi All,
Please find below more information regarding the same as asked..
There is a PLL, its output clock is divided down by an "OUTPUT DIVIDER"and used as clock for an application(s).
Now, the application uses both rising and falling edges of the clock it is provided with and the clock needs to be of 50% duty cycle.
The application needs different clock frequencies in different scenarios (now, one might think that this change in frequency can be achieved by varying PLL frequency but I cannot do this due to other system level reasons). So, I need an output divider whose division value can be changed i.e. a multi modulus divider. This is usually implemented using div 2/3 cells (divider that can divide by 2 or 3 based on an input control) in cascade e.g. shown on slide 34, 35 and 36 of the MIT lecture mentioned by Erikl. Now the problem with this approach is that the output is not 50% duty cycle. So, I would like to know if there is a way to tweak the design example or some other topology which would give 50% duty cycle.
e.g. I have a PLL wiht 2GHz output, from this i need to generate two clocks one at 2GHz/20 and the other is 2GHz/21 but both need to be 50% duty cycle.
Any suggestions please..
Thank you,
mvj