[MOVED] Design of 14-bit DAC: Capacitive+ Resistive DAC vs. Purely Resistive DAC?

[centaurus01]

There are 2 options of 14-bit DAC on a full range of 1.2V that we are trying to implement:

a) Using 8 bits on a R+MOS DAC (5 bits on RDAC and 3 on MOSDAC) and other 5 bits (MSBs) on the capacitive DAC. Last bit (MSB) is a sign bit. S/H circuit is used to charge the output.
b) Using 14 bit R+MOS DAC (8 bits on RDAC and 6 bits on MOSDAC).

From bench data of past performances, option a is not much better than option b. Theoretically, cap DAC is supposed to improve INL due to better matching and reduce current and area consumption. However, both DNL and INL is similar for both option a and option b. Area and current is also similar.

I will be grateful if you could give your views on following questions:
1. Is it better to implement Capacitive DAC on LSB and RDAC on MSB for option a?
2. kT/C noise analysis gives me a value of noise to be 100uV for 400fF cap. But LSB itself is 72uV. Will increasing the size of cap increase performance?
3. Any other architecture that we can try which will be good for high performance, high resolution DAC?

Thank you!

 

[BradtheRad]

The range for 14 bits is 16,384. Your voltage range is 1.2V. This puts your LSB close to the noise floor.

If you increase your upper voltage, it will also raise your distance above the noise floor.

Then you would divide down the output (maybe with a resistor network). I don't know how easy it would be to prevent introducing other noise however.

 

[centaurus01]

Thanks! Indeed the noise floor is too close to LSB.
But do you think making RDAC as MSB and Cap DAC as LSB will make the noise performance better?
Also, for the noise analysis of R, the formula is 4kTR.BW. What is the noise BW to be used for analysis?

 

[BradtheRad]

Sorry, my only experience is with 8 bit DAC (resistor network). I'm sure your knowledge exceeds mine.