Yes ASICS, they've used the ring oscillators using the combo loop logic and as I said, it works on silicon without an issue.... However I agree that they will loose stuck-at coverage because the DFT guys will not be able to observe the stuck-at gates which are in the vicinity of this gate.....
Thanks for the reply..... I want to know how did that happened , how come they've taped out successfully ? My requirement is simpler I want to generate a stable combo loop , It doesn't fluctuate at all (Stuck-at kind of ckt) ? Can I go ahead to implement it and run it out without an issue ? (even on silicon)
There are stable loops, an OR gate with one of its inputs controlled, and the other input is connected to output(combo loop) , so once an I/P 1 is given the OR gate gets stuck-at-1 and this is what people call as a stable loop.
I also don't understand what is that you are calling a stable combo loop. That statement is wrong by definition. Combo loops are not stable.
A DFF is comprised of two latches (= combinational loops) in master-slave configuration on the transistor level. In so far I don't understand the generalized statement about unstable combinational loops.
The most common non-trivial example that I know of is the ones-complement adder. In this circuit, the carry-out of the last stage is fed to the carry-in of the adder. This circuit does not oscillate continually nor does it result in a memory effect.
I agree as a general rule, but can't agree with the generalized statements about combinational loops being basically unstable.Bottomline is, don't design digital ASICs with combo loops.
Don't see the difference of "sequential" versus "combinational" loop. The DFF macro has combinational loops.That is a sequential loop, which is ok.
The most common non-trivial example that I know of is the ones-complement adder. In this circuit, the carry-out of the last stage is fed to the carry-in of the adder. This circuit does not oscillate continually nor does it result in a memory effect.
What are the consequences of having a latch in the design , does it create a problem in the circuit ? Are they synthesizable ? If Yes, what precautions should I take to implement a latch in my design ?
Firstly, if we use such a combo loop , the OR gate gets stuck-high and the DFT engineers will remonstrate , because all the stuck-at-faults in the vicinity of this OR gate will not be observed. Hence, they will loose their stuck-at coverage, Plan to have a flop in between and this design will pass the litmus test.
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