rekhavp
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I have written a VHDL code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. If any one know how to fix this please help me . It is urgent. I'm attaching the code with this.
package body
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package body
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 ------------------------------------------------------------------------------------------- -- Package File Template -- -- Purpose: This package defines supplemental types, subtypes, -- constants, and functions library IEEE; use IEEE.STD_LOGIC_1164.all; package pack_puf is constant m : integer :=3; type row_bit is array (m downto 0) of bit; end pack_puf; -------------------------------------------------------------------------------------------- main body ----------------------------------------------------------------------------------------- ---------------------------------------------------------------------------------- -- Company: -- Engineer: -- -- Create Date: 20:30:06 09/30/2014 -- Design Name: -- Module Name: cascaded_puf - Behavioral -- Project Name: -- Target Devices: -- Tool versions: -- Description: -- -- Dependencies: -- -- Revision: -- Revision 0.01 - File Created -- Additional Comments: -- ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use WORK.pack_puf.all; use IEEE.numeric_std.all; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity cascaded_puf is generic(lngth:integer:=3); Port ( I,J : in bit; C : in row_bit; P,Q : out bit); end cascaded_puf; architecture Behavioral of cascaded_puf is begin process(C) variable temp1:row_bit; variable temp2:row_bit; begin if(C(0)='0') then temp1(0):=I; temp2(0):=j; else temp1(0):=J; temp2(0):=I; end if; for i in 1 to lngth loop if(C(i)='0') then temp1(i):=temp1(i-1); temp2(i):=temp2(i-1); else temp1(i):=temp2(i-1); temp2(i):=temp1(i-1); end if; end loop; P <= temp1(lngth); Q <= temp2(lngth); end process; end Behavioral;
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