Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] [Moved]: analog filter input/output termination match

Status
Not open for further replies.
Maybe something is not mentioned. The original designer of this circuit is not with this group any more, so I have to guess what they are doing.
Apparently the major problem is that the purpose and specification of the filter are not really clear. How can we help in this case?

If you know the specification, why not redesign the filter from the scratch?
 

I am designing a filter with a notch at 800MHz to block interference .

If you are working at 800 MHz, you had better have a darned good idea what the source and load impedance of your circuit is, or you will be doing a VERY poor design.
What are you driving this filter with, and what are you loading this filter with.
 
Apparently the major problem is that the purpose and specification of the filter are not really clear. How can we help in this case?

If you know the specification, why not redesign the filter form the scratch?

Hi, FvM:

I think I can actually mark this question as solved because with the help from all the replies, I have found the meaning of impedance matching as my previous reply shows. I don't intend to push the question further as how should I design this filter to satisfy all requirements. From the scope of this post, I think I have achieved what I want to know.

But if someone can tell me a bit more regarding the relationship between the narrow band LC matching networking nature with designated LC filter having broadband frequency passing features, I will really appreciate it. More specifically, as the S11 or smith chart shows, there is only one frequency have pure resistive impedance while all the other frequency has kind of impedance mismatch. Based on the concept of power factor, it means besides signal on that specific frequency, all other signal frequency components will cause extra current flowing or signal reflection in the circuit to distort the time domain waveform.

What does the spec should look like? For example, how much attenuation should S11 have at certain frequency? How can I figure it out based on system requirement if the proper system designer has not been hired.
 

If the load is not matched, the source needs to provide reactive power besides the active power, increasing then the total RMS currents in the circuit, hence losses. Matching the load gets rid to the reactive power and hence less stress is taken from the supply and less stress (in terms of RMS currents) is on the circuit elements.
Matched load means only active power is supplied.

Hi CataM:

Do you mind share me more thoughts regarding the broadband load matching? as the LC circuit can only match at one frequency while my design will be from baseband to 400MHz.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top