mostly used verification language in industries?

[abhineet22]

please tell me which language is used
1.vera
2.systemc
3.systemverilog
4.tcl/tk
or some thing else

 

[bigyellow]

I do not think systemc and system verilog are very popular in industry right now. They need some time to be accepted.

 

[au_sun]

i think SYSTEMVERILOG has come with powerfull features af all other HDL and HDV languages lack, it is one of most used one,
SYSTEMC and VERA also has a very important part in the VERIFICATION

but u have missed one language E-LANGUAGE its also one of most used one of verification language

 

[sarath51]

Presntly most of the verification enviroenmetns are built in verilog, C , vera and e , E presently has more usage thatn vera but still people are using verilog and C as a part of tyheir verification, but the future seems to be more towrds Systemverilog than systemc

 

[quake]

Yeah, "au_sun" is right, SystemVerilog has become the most advanced verification
tools nowadays, VIA are using it. But the tools seems expensive. Its is so powerful
and are more preferable than E and Vera. SystemVerilog is the trend.

 

[maxsnail]

in Synopsys 2005 semiar, it have a new verification methodolgy, it use some language involved from vera

 

[JesseKing]

systemverilog, ok

 

[wangkl]

I still use verilog mostly.

 

[andromeda]

Majority of verification environments used around are Verilog + C. Companies spend lot of time and efforts in developing of verification methodologies and they don't want to transit to anything, if they really don't need.
The only way to go to 'new' constraint-random verification philosophy is to realize that the good, old directed tests method doesn't work anymore. But companies has a lot of engineers used to directed tests (which spend majority of time in maintening of huge amount of directed tests and generating 'great' regression reports) and lot of managers which don't want to risk.
Also, verification isn't area independent from the rest of chip development - there is SW/HW partitioning (in average, there is several CPUs on any ASIC today), SW/HW codesign/coverification. SystemC has great advantage that it is natural for SW/HW codesign/coverification, but also has big misadvantages (over Vera and e) that functional coverage tool support doesn't exist.
In company I am working with (big one), we are using SystemC/Verilog cosimulation, on the last project (before it was Verilog/C). Still we are using directed test methodology with some custom made functional coverage (for type of application we are working on, it is suitable).

It looks to me that SystemC/SystemVerilog cosimulation will be verification environments of the future. Subset of Vera is anyway in SystemVerilog and it is clear that Synopsys is forsing second one. It is not clear still, what Cadence plan to do with their Vericity acquizition - they are main force behind SystemC. Nobody will use 3 languages (Verilog+e+SystemC) for whole design/verification process, so who know what are their plans.

 

[roger]

in Synopsys 2005 semiar, it have a new verification methodolgy, it use some language involved from vera

vera is not an open standard, except SYNOPSYS , who is going to support?
will SYNOPSYS donate it to IEEE or promote vera? seemed impossible.

 

[marksile]

I use verilog mostly. It's no important that you use the sort of verification language, I think that you like that verification language.

 

[yasonwang]

SystemVerilog combines VERA and superlog.

It is a successor from VERA.

 

[chaitu2k]

could anyone tell whts best with modelsim....is tcl/tk the most supported by modelsim or whts better

thnks

 

[sriramsv]

I think systemverilog and systemc are statred to be preffered in the industries

 

[gaonkc]

we use verilog and verilog-a to verify .

 

[tutx]

For me, synnopsys is usually used. However, today many designers try to replace it by SystemC.

 

[bigyellow]

we still use VHDL

 

[shelkerahul]

It is true, the most powerfull language is "systemverilog", But not mostly used.

I think mostly used language is 'SYSTEMC'

 

[linuxluo]

hi,
tcl/tk is not verification language.
vera/e/sugar are nowadays language . the next will be systemC and systemVerilog.
systemVerilog is from vera&superlog.
but I think systemC maybe more popular.

 

[skymusic]

Specman is powerful to auto verify tools. E is its language.