Majority of verification environments used around are Verilog + C. Companies spend lot of time and efforts in developing of verification methodologies and they don't want to transit to anything, if they really don't need.
The only way to go to 'new' constraint-random verification philosophy is to realize that the good, old directed tests method doesn't work anymore. But companies has a lot of engineers used to directed tests (which spend majority of time in maintening of huge amount of directed tests and generating 'great' regression reports) and lot of managers which don't want to risk.
Also, verification isn't area independent from the rest of chip development - there is SW/HW partitioning (in average, there is several CPUs on any ASIC today), SW/HW codesign/coverification. SystemC has great advantage that it is natural for SW/HW codesign/coverification, but also has big misadvantages (over Vera and e) that functional coverage tool support doesn't exist.
In company I am working with (big one), we are using SystemC/Verilog cosimulation, on the last project (before it was Verilog/C). Still we are using directed test methodology with some custom made functional coverage (for type of application we are working on, it is suitable).
It looks to me that SystemC/SystemVerilog cosimulation will be verification environments of the future. Subset of Vera is anyway in SystemVerilog and it is clear that Synopsys is forsing second one. It is not clear still, what Cadence plan to do with their Vericity acquizition - they are main force behind SystemC. Nobody will use 3 languages (Verilog+e+SystemC) for whole design/verification process, so who know what are their plans.