Hello people,
I was doing current mirror simulation on LTSpice and i realized by changing the mosfets width its threshold voltage is actually changes, not so much but a little. I wonder what is the reason for that. What equation do i consider to understand this effect.
Thanks in advance.
There are many "VT" measurements and the "true VT" itself
(the extrapolated saturation sqrt(Id) X-intercept) can vary
in more aggressive technologies due to lithographic / strain
effects.
VT1uA will certainly move with changes to width because it
is a fixed measure-at against an external reference. Others
like VTlin, VTsat ought to be "dimensionless" and first-
order-invariant (although L also may play, short channel
and bias effects may make VTsat vary more with drain
voltage, than VTlin).
I'm some how curious why your gate voltage is higher than your complience volgate of 5 V (VDD). Define your current source as active load should result in a gate voltage smaller than 5 V.
This effect in MOSFETs is called "narrow channel effect" - where threshold voltage gets larger as gate width gets narrower.
(the direction of this effect is opposite to "short channel effect" - where Vt gets lower for shorter gate lengths).
Physically, narrow channel effect is caused by the 2D shape of the depletion region, requiring a higher gate voltage to reach the inversion condition in the channel.
Technology advances has enabled reduction in transistor dimensions to almost nm scale dimensions as low as 25 nm. CMOS circuits designed for deep submicron technology have imposed new design challenges called as submicron or second order short channel effects (SCE). These SCE contribute to...