Why Threshold voltage of PMOS decreases when reduce the width?

[mpig09]

Hi all:

I design a PMOS current mirror, and the current ratio is 1:2:4:8.

There are two kinds of width ratio to get 1:2:4:8. (the same L=2.8u, Process is 0.153um)
1st : MB61A, W=0.36u 2nd: MB61B, W=0.36u, m=1
MB62A, W=0.72u MB2B, W=0.36u, m=2
MB63A, W=1.44u MB63B, W=0.36u, m=4
MB64A , W=2.88u MB64B, W=0.36u, m=8

The simulation shows the IMxA < IMxB (ex: IMB64A < IMB64B)
and Vth, MxA > Vth, MxB.

Please the attached file for hspice .lis.

My question are :
1. why Vth, MxA > Vth, MxB?
ex : Vth, M64A > Vth, M64B.
2. Why IMxA < IMxB
ex: IMB64A < IMB64B


Thanks.
mpig

 

[mpig09]

Hi all:

It is "inverse narrow width effect, INWE"

What's cause INWE?

Thanks.
mpig

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[dick_freebird]

Edge effects modeled as deltaW

 

[timof]

In the past, Vt of MOSFET was increasing (by absolute value) for decreased gate width.
In later technologies, it goes in the opposite direction, that's why it's called inverse narrow channel effect.

It's not clear how deep into device physics you want to go, to view it as an acceptable answer.