Hello ashare -
Your transistor "L" value will be determined by the maximum source-drain voltage that this transistor should withstand.
In high voltage processes, this value would be fixed, for a given breakdown voltage.
Your W will be determined by the conduction losses P=Rdson*I^2 (times duty cycle ratio for that device), or, more precisely, by a proper balance of the conduction versus switching losses.
Conduction losses scale with W as ~1/W, while switching losses (gate charging losses - to be more precise) are proportional to "gate capacitance" and thus scale as ~W.
In DC-DC converter, transistor operates at low Vds and high (nominal) Vgs, so it is in the linear part of MOS I-V curve.
Usually, when designing a DC-DC converter, people build a spreadsheet model that would account for static and dynamic (switching) losses for high side and low side transistors, diode reverse recovery loss, and many other power loss sources (inductor series resistance, metal interconnects and wirebond/package resistance, ringing losses). Various factors would be parameters of this model - input and output voltages (and thus duty cycle ratio), switching frequency, temperature, load current, etc. This model is not very precise, but would capture the main power loss mechanisms, and would allow some analysis and optimization.
Then, plots of converter efficiency versus various parameters are generated, and optimum design point is decided (most importantly - W for low side and high side transistors).
Quite often, the power efficiency is strongly affected by factors outside the power chip - like package and board parasitics (most notably - parasitic inductance), placement of decoupling capacitors, etc. - but that a subject for a separate discussion.
Max
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