[SOLVED] Mosfet W/L ratio for DC-DC converter

[ashare]

Dear All,

I am planning to design of a DC-DC Buck-Boost converter in Global Foundries 180n process. Could anyone advise me what is the starting point to derive the MOSFET W/L ratios required for the design. I understand that the MOSFETs used should be able to handle the current for which I am designing the converter. In that case, should I be using the large signal triode equation for the MOSFET? Also, how can I achieve a W/L ratio which is more suitable for such kind of application considering there are conduction losses as well as switching losses. Is there any tool inside Cadence which can directly give me the switching and conduction losses?

Thank You.

Regards,
ashare

 

[timof]

Hello ashare -

Your transistor "L" value will be determined by the maximum source-drain voltage that this transistor should withstand.
In high voltage processes, this value would be fixed, for a given breakdown voltage.

Your W will be determined by the conduction losses P=Rdson*I^2 (times duty cycle ratio for that device), or, more precisely, by a proper balance of the conduction versus switching losses.
Conduction losses scale with W as ~1/W, while switching losses (gate charging losses - to be more precise) are proportional to "gate capacitance" and thus scale as ~W.

In DC-DC converter, transistor operates at low Vds and high (nominal) Vgs, so it is in the linear part of MOS I-V curve.

Usually, when designing a DC-DC converter, people build a spreadsheet model that would account for static and dynamic (switching) losses for high side and low side transistors, diode reverse recovery loss, and many other power loss sources (inductor series resistance, metal interconnects and wirebond/package resistance, ringing losses). Various factors would be parameters of this model - input and output voltages (and thus duty cycle ratio), switching frequency, temperature, load current, etc. This model is not very precise, but would capture the main power loss mechanisms, and would allow some analysis and optimization.
Then, plots of converter efficiency versus various parameters are generated, and optimum design point is decided (most importantly - W for low side and high side transistors).

Quite often, the power efficiency is strongly affected by factors outside the power chip - like package and board parasitics (most notably - parasitic inductance), placement of decoupling capacitors, etc. - but that a subject for a separate discussion.

Max
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[ashare]

Thank You, Max for the detailed explanation. Could you please answer the following questions as well?

Your transistor "L" value will be determined by the maximum source-drain voltage that this transistor should withstand.
In high voltage processes, this value would be fixed, for a given breakdown voltage.

Can this be obtained from the Foundry data?

Also, could you tell me how do we decide the minimum W value which can handle the current I intend to pass through the transistor? Do I need to use the equation Id= u*Cox*W/L*[(Vgs-Vt)-Vds/2}*Vds given the current consumed by the load and having known L value from the data above?

Thank You.

Regards,
ashare

 

[timof]

Thank You, Max for the detailed explanation. Could you please answer the following questions as well?



Can this be obtained from the Foundry data?

Also, could you tell me how do we decide the minimum W value which can handle the current I intend to pass through the transistor? Do I need to use the equation Id= u*Cox*W/L*[(Vgs-Vt)-Vds/2}*Vds given the current consumed by the load and having known L value from the data above?

Thank You.

Regards,
ashare

The breakdown voltage (which should be equal or higher than input and output voltages) should tell you what device type you should use, not the L - for example, NLDMOS24, or PLDMOS40, etc.

Then, you can use a SPICE compact model for that device type, to simulate I-V characteristics, calculate its specific channel resistance (channel resistance per micron of gate width) for the ON state, etc.

Also, quite often, foundry provide data on device specific resistance - either in the units of Ohm*um (i.e. resistance per micron of gate width), or Ohm*cm2 - resistance per unit area - that can be converted to units of Ohm*um by dividing by the value of finger pitch.

 

[ashare]

Thank You, Max.

Regards,
ashare