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MOSfet , the operation of sub-threshold region

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020170

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in cadence, MOSfet is usally operating in sub-threshold region, region = 3 , especially 0.18um Fabrication process.

I want to know what is your thought about the operating of MOSfet in the sub-threshold region.

Some circuit is operating in the sub-threshold region in cadence, But when I extract it from cadence to Hspice netlist and then simulated in Hspice, it resulted in that operationg in the Cut-off region, Because Hspice didn't know sub-threshold region!

but DC Bias point and current is same value in Cadence.

But I don't know whether I believe cadence's result or Hspice's result.

and also I don't know that I can trust my circuit's operation in the sub-threshold region


how about your opinion?

thanks
 

v_c

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Take a look at Section 7.7.4 to see if this impacts your design.

https://ece-www.colorado.edu/~bart/book/book/chapter7/ch7_7.htm

If you simulator is not taking care of this, then your leakage current
calculations might not be accurate. See the following

Subthreshold leakage is the current that flows from the drain to source of a MOSFET when the transistor is supposed to be off.

In the past the subthreshold leakage of transistors has been very small, but as transistors have been scaled down, subthreshold leakage can compose nearly 50% of total power consumption. The reason for this is that the supply voltage has continually scaled down to reduce the dynamic power consumption of integrated circuits (the power that is consumed when the transistor is switching from an on-state to an off-state) which depends on the square of the supply voltage. As the supply voltage is scaled down, to maintain performance, the threshold voltage has to be reduced in the same proportion. As threshold voltages are reduced, subthreshold leakage rises exponentially.

Best regards,
v_c
 

    020170

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