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# MOSFET question: what is the maximum voltage of capacitor?

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#### rogger123

##### Advanced Member level 4
tricky question in tagalog

Hi guys,
In the attached diagram, what is the maximum voltage the capacitor would charge to. The gate is tied to 5V the Drain is connected to 3V the capacitor is connected to the Source of the nmos with Vt=1V.
I was told the capacitor would charge to 4V but i dont understand how.
Could someone elaborate.

Rgds
Rogger

Re: MOSFET Tricky Question

If drain is connected to 3V capacitor cannot be charged higher than 3V.
You can bet with person who told you, make an experiment and win.

Re: MOSFET Tricky Question

I think fom is right! there is no way capacitor can cross max 3v!

Re: MOSFET Tricky Question

no way more than 3 v .............

Re: MOSFET Tricky Question

The more interessting question is if you interchange the 5V with the 3V and ask again!

Re: MOSFET Tricky Question

I suppose if the supplies were interchanged then the capacitor would charge to 4V.
Regardign the first scenario is there a possibility of the gate to source capacitence to play a role in allowing the voltage to go beyond 3V.

Rgds
Rogger

MOSFET Tricky Question

ya it wont cross 3V

Re: MOSFET Tricky Question

Regardign the first scenario is there a possibility of the gate to source capacitence to play a role in allowing the voltage to go beyond 3V.

Only if you precharge gate, then leave it floating and after that change drain voltage from 0 to 5V.
In this case source capacitor can be charged up to 5V too. But at the same time gate voltage will be boosted may be up to 7V.

First dynamic RAM devices included only NMOS transistors (No PMOS) and they operated in this way.

Re: MOSFET Tricky Question

It is true that for the circuit shown, the capitor will charge to 3V. However, if we interchange the power supplies by connecting 5v to gate and 3v to drain, then the capacitor would charge to only 2v.

Re: MOSFET Tricky Question

Remember that the Mos is ON (triode or sat) under two conditions
A must condition: Vds > 0
Another cond: Vgs >= Vtn

The Capacitor keeps charging towards the supply on the left (and regards the MOS as a resistance that is linear in triode and non-linear in sat) till the MOS is off, so in the diagram you posted it will reach 3 v and after that the MOS is an Open Circuit because Vds <= 0.
If the supplies are interchanged, the Cap charges towards 5v as a final voltage, yet the Mos cuts off when it reaches 2v because Vgs then is equal to Vtn.

Hope you got it now :?:

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