MOSFET MODELL: Total Gate Charge effect

[caledonia]

Hello


I would like to simulate a simple circuit with a current Mirror built with NMOS Transistors.
To test the linearity of the circuit accuratly I would like to take also the variation of the Gate capacity with the Voltage, called the Total charge effect, into account.

Have you any idea how this dependency can be expressed?

thank you!

 

[erikl]

To test the linearity of the circuit accuratly I would like to take also the variation of the Gate capacity with the Voltage ...

Mirror current linearity is a DC analysis result, any capacitances have no effect on current linearity -- they just play their role in AC or transient analyses.