Hi,
T21 is on. Causing your current ...
Erm... Why do you say that? While I'm sure you're right, the simulations give T21 gate voltage as 104mV or at worst 184mV when Vin is an OTT 35V.
I checked this several times last night before posting the question, and to do my due diligence I've checked this again and again this evening to try to understand what you mean but e.g. at V in 10.4V the PMOS gate is at 10.3V, 1uA and the NMOS gate at 49mV.
I would be quite confident saying that in no way is that NMOS on, it needs at least 0.6V to do anything according to the datasheet (simulation of NMOS on own as follower allegedly needs 1.2V to turn on, close to worst case datasheet specs of 1.5V).
At 10.2V the PMOS is gate is in the 200uV range and the NMOS gate in the 10V range but that is clearly not the problem, the PMOS output supposedly rises with rising input voltage and it should do the opposite.
The above are results from the "DC analysis: Calculate nodal voltages" simulation(s), the graphs from yesterday are "DC transfer characteristic, (V in 0V to 35V)". Either analysis - whichever version of the comparator used - shows the comparator output at ~100mV when it goes low.
Really appreciate the reasoning for the comment, thanks, because it puzzles me and I value your experience. Is there any chance the simulator is interpreting gate breakdown as both devices are limited to -10V and 12V, something I find unlikely?