Charge injection cancellation can be tricky, the Qinj
depends on both the capacitance and the common
mode position (dQ=CdV, neglecting the nonlinearity
of C) and where the M1 (ref above post) gate charge
goes, on turnoff, is also pretty variable with the
internal and external impedances, as far as the
partitioning of gate charge between S, D, B.
In the above example, M2 supplies (Cgs+Cgd)*dVph1_
but M1 may push only Cgd*dVph1 toward C1, with
Cgs*dVpgh1 going back out the input. This might
-overcompensate- the charge injection. This can
be tweaked, and it may be better to use two half
(*) FETs, one before and one after the switch.
* give or take - tweak ratio to suit, given expected
application and test conditions
In designing S/H products I've found it useful to
make adaptive switch gate drive that takes the gate
to no more negative (N) or positive (P FET) than it
takes to get to "off". This minimizes "off" transition
overtravel and C*V charge. Of course then you need
level shifters and biases and on chip decoupling, and
all of that has to slew with the input voltage (so a
buf amp at minimum and had better track and settle
fast).
Re on resistance, classical low field mobility ratio is
not the whole deal in modern, highly "drain engineered"
MOS technolgies - the on resistance may be dominated
or at least significantly bent by the LDD and halo regions
which act as minuscule JFETs in series with source and
drain. In a "digital" flow you are almost certain to see
this (some RF and analog flows offer a non-extended
"analog" device that gives better linearity and lower on
resistance, at perhaps the cost of longer min L or lower
application voltage rating). You probably want to tune
by simulation, provided that you believe the foundry
device models are decently fitted for both channel and
access (extension*halo) behavior.