MOS size in different driving

[john7796]

Dear All,

I am a digital designer, I have no sense on circuit design. But I need the information following, please help me. And Feb's data is ok.

1. In 0.18um process, when the driving current is 100uA, how small the MOS transistor could be? (0.18um process)
2. In 0.18um process, when the driving current is 10uA, how small the MOS transistor could be? (0.18um process)
3. In 0.18um process, the metal line has 64um long and 0.5um width, what is the capacitance and resistor value?
4. In 0.18um process, if implement the 1000Ω resistor, how small the MOS transistor could be?

John

 

[erikl]

1. In 0.18um process, when the driving current is 100uA, how small the MOS transistor could be? (0.18um process)
2. In 0.18um process, when the driving current is 10uA, how small the MOS transistor could be? (0.18um process)

For both cases, all process limited values (both min. & max.) stated by the fab/foundry are possible.

3. In 0.18um process, the metal line has 64um long and 0.5um width, what is the capacitance and resistor value?

Depends on which metal level is used.

4. In 0.18um process, if implement the 1000Ω resistor, how small the MOS? transistor could be?

Depends on which resistor layer is used.

 

[john7796]

Dear erikl,

Could you give a reference value?

I need value to calculate. Thanks a lot.

John

 

[erikl]

Could you give a reference value?

For 10µA you could e.g. use a min. W/L ratio of 1 (i.e. 0.18µm/0.18µm) with an overdrive voltage of ≈350mV working in strong inversion (Inversion coefficient IC=20),
or e.g. a large W/L ratio of 20 (i.e. 3.6µm/0.18µm) with an overdrive voltage of ≈30mV working in medium inversion (Inversion coefficient IC=0.7).

For 100µA you could also use a min. W/L ratio of 1 (i.e. 0.18µm/0.18µm) with an overdrive voltage of ≈1V working in very strong inversion (Inversion coefficient IC=200),
or e.g. a very large W/L ratio of 200 (i.e. 36µm/0.18µm) with an overdrive voltage of ≈30mV, again working in medium inversion (Inversion coefficient IC=0.7).

Metal to GND capacitance lies between 40 and 120 aF/(µm)^2 , the lower metal levels owning the larger values, of course.
Hence a metal line of 32(µm)^2 will have a capacitance between 1.3 and 3.8 fF .
With 0.08Ω/⃤ , its resistance would be 10.2Ω .

A 1000Ω resistor, if you use a poly resistor with e.g. 400 Ω/⃤, could be min. 0.45µm/0.18µm (if no matching is necessary).

 

[john7796]

Dear Erikl,

Thanks a lot for your reply.

1. If 1000Ω resistor consists of MOS transistor, how small the MOS transistor could be?
2. Could you tell me the difference between strong inversion and medium inversion?


John

 

[erikl]

1. If 1000Ω resistor consists of MOS transistor, how small the MOS transistor could be?

You could manage this with a min. size MOSFET with correct bias. However, even this min. size MOSFET - not to mention the required bias generation - would need more space than the poly resistor - and would show a much larger temperature dependence.

2. Could you tell me the difference between strong inversion and medium inversion?

I think this would be too extensive to be discussed in a forum. You better study this in a good textbook on analog circuit design; for this topic I'd clearly suggest David M. Binkley: "Tradeoffs and Optimization in Analog CMOS Design".

 

[john7796]

Dear Erikl,

Do you know inversion coefficient in standard cell ?

John

 

[erikl]

I think you're speaking of logic ("digital") standard cells? In this case the transistors are always operating in very high inversion mode (IC > 100).

 

[john7796]

Dear Erikl,

Thanks a lot.
Is high inversion mode will make layout area larger or without relationship at layout area?

John

 

[erikl]

In "digital" cells you always work with large (i.e. nearly the full supply voltage range) input voltage(s) and the same is valid for the output voltage(s) - so no amplification has to occur (means: no "analog" requirement). This means you use min. size input transistors, whereas the output transistors are scaled for their fanOut resp. drive requirements - so there's no relationship between inversion mode and layout area.

Anyway: Necessary layout area is inversely proportional to the inversion mode the transistor is to be operated in. I.e. for analog cells: As lower its inversion coefficient operation mode, as higher its W/L and so its layout area demand.

BTW: You could learn all these contexts from reading the a.m. book!