Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

MOS Parasitic Capacitance Calculation in Cadence Spectre

Status
Not open for further replies.

Elecemperor

Junior Member level 2
Joined
Apr 11, 2015
Messages
22
Helped
1
Reputation
2
Reaction score
1
Trophy points
3
Activity points
211
I want to design a circuit in which parasitic capacitors are very important, and I'm trying to derive some formula which necessitates calculating these capacitors by a specific equation (and not just simulating and checking their value every time). Is there any such equation? Specially for Cds.
 

erikl

Super Moderator
Staff member
Joined
Sep 9, 2008
Messages
8,112
Helped
2,686
Reputation
5,352
Reaction score
2,284
Trophy points
1,393
Location
Germany
Activity points
44,153
As long as you don't know the connection lengths between the individual devices in layout, you can't even make a reasonable estimation.

If you can draft a schematic which reasonably would mirror the expected lengths of the future layout connections, you could measure the connection lengths and calculate their anticipated mean values on a Cp/µm (and, if necessary Rp/µm) basis of the used process.

You can get these figures e.g. from the ITRS Reports; use the global wire values. Cap/length values do not depend too much on process size; for such a rough estimation you can use 0.2fF/µm.

This could result in a very, very rough estimation.

If you want, try this and compare with results from an extracted layout.
 
Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top