Usually, accumulation layer formed by holes (in nMOS transistor) is not called a "channel" - a channel is something that allows a current flow between source and drain.
When AC signal is applied to the gate, capacitive current for an MOS transistor in accumulation region will flow mostly to the bulk, so gate capacitance will be determined (mostly) by Cgb - gate to bulk / substrate capacitance.
There may be some capacitive current flowing form the gate to source / drain - through overlap capacitance, or gate to source/drain contact capacitance (high in scaled technologies, and especially - in FinFETs!), or through bulk-to-source/drain capacitance.
So Cgd and Cgs, while being lower than in inversion region, are not zero.