Stepan Sutula
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Hi,
During the Spectre netlist generation process, I have found out that the netlister includes the parasitic resistances of the MOS transistor bulk routing in the resulting netlist like:
rg58 (vdda \5\:vdda) resistor r=24.5376 c=0
But, it skips connecting this parasitic resistor to the bulk of the transistor:
M10 (\3\:vout \5\:nclk \2\:vin vdda) p_lv_18_mm w=1.92e-06 l=2.4e-07 ad=2.224e-13 as=2.224e-13 pd=2.0u ps=2.0u m=(1)*(1)
From the line above, you can see that it circumvents the parasitic resistor and connects the bulk directly to the polarization net vdda (NOT \5\:vdda that I have been expecting from my av_extracted view).
Is there any way to fix this problem?
I'm using Virtuoso Design Environment version IC6.1.3.500.13 with Assura 3.2OA lnx86 (Cadence Extraction QRC - Parasitic Extractor - Version 8.1.4-p002).
Thanks,
Stepan.
During the Spectre netlist generation process, I have found out that the netlister includes the parasitic resistances of the MOS transistor bulk routing in the resulting netlist like:
rg58 (vdda \5\:vdda) resistor r=24.5376 c=0
But, it skips connecting this parasitic resistor to the bulk of the transistor:
M10 (\3\:vout \5\:nclk \2\:vin vdda) p_lv_18_mm w=1.92e-06 l=2.4e-07 ad=2.224e-13 as=2.224e-13 pd=2.0u ps=2.0u m=(1)*(1)
From the line above, you can see that it circumvents the parasitic resistor and connects the bulk directly to the polarization net vdda (NOT \5\:vdda that I have been expecting from my av_extracted view).
Is there any way to fix this problem?
I'm using Virtuoso Design Environment version IC6.1.3.500.13 with Assura 3.2OA lnx86 (Cadence Extraction QRC - Parasitic Extractor - Version 8.1.4-p002).
Thanks,
Stepan.