[SOLVED] monitoring post-layout signals/buses

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dave9000

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Hi all,

in pre-layout I am using a non-synthesizable monitor component to dump to file the opcodes executed by an embedded CPU.
In post-layout I lose the dump (I enveloped the monitor code in translate_off pragmas).
Also I don't have enough spare pins to move the monitor outside the design top, to the test-bench.

Is there a way in modelsim to pass/copy/alias some internal signals to a testbench component?
Any idea?
Thanks.
 

Hi Deve9000,
I would like to know a few things,
1. which HDL are you using? if verilog then its possible to monitor internal signals while doing simulation.
2. If its a testbench and your doing simulation in Modelsim, then why pin is the constraint.

GCK
 

hi gck, thanks for your reply!
I am working with VHDL.
I have a problem with pins because I would like to run a post-layout simulation while monitoring some ~200 internal signals - and I don't have all those spare pins.

In the end I've been given two useful hints from a collegue of mine.
I'm posting the hints here, 'cause they may be useful to someone else.

[The first] Using enable_signal_spy from the modelsim_lib library. This function actually connect two signals from anywhere in the design hierarchy:
Code: 
library modelsim_lib;
   use modelsim_lib.util.all;
.....
   init_signal_spy("/tb/uut/some_internal_signal", "/tb/tb_signal");

[The second] Using the SIMBUF buffer - for Actel only.
This buffer is removed by the place-and-route tools but is re-inserted in the post-layout simulation files.
 
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