mjuneja
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I want to implement modulus or reminder operation in FPGA using VHDL for 2 unsigned nos. I tried using below code.
but got the following error :-
Thanks
Madhur
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 process(clk,rst,pxl_1,pxl_2,DV) begin if(rst = '0') then pxl_o2 <= (others => '0'); elsif(rising_edge(clk)) then if(DV = '1') then pxl_o2 <= std_logic_vector(unsigned(pxl_1) mod unsigned(pxl_2)); end if; end if; end process;
but got the following error :-
Can anyone help me out with some alternate implementation of modulus operation.: Operator <MODULUS> must have constant modulo operand.
Thanks
Madhur
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