clavin
Newbie level 4
i am making a vhdl code for finding remainder
i know there is a mod operator but still i am making the following program
the problem is suppose i divide 4 by 3 so in this case i have to subtract 4 by 3 only once so the program shows the necessary output
but lets say a loop is needed (for which i am trying to use the state) in that case the answer is not coming
i want to execute the code without for, while, etc loops but using states
so pls if possible do not suggest loops
i know there is a mod operator but still i am making the following program
the problem is suppose i divide 4 by 3 so in this case i have to subtract 4 by 3 only once so the program shows the necessary output
but lets say a loop is needed (for which i am trying to use the state) in that case the answer is not coming
i want to execute the code without for, while, etc loops but using states
so pls if possible do not suggest loops
Code:
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:14:25 11/10/2011
-- Design Name:
-- Module Name: divi - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity divide is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
done: out std_logic;
d : in std_logic_vector(6 downto 0);
c : in STD_LOGIC_vector(6 downto 0);
remainder : out integer range 0 to 127);
end divide;
architecture Behavioral of divide is
type state_type is (s0);
signal current_s,next_s: state_type;
begin
process (clk,reset)
begin
if (reset='1') then
current_s <= s0;
elsif (rising_edge (clk)) then
current_s <= next_s;
end if;
end process;
process (current_s , c,d)
variable int1 : integer range 0 to 127;
variable int2 : integer range 0 to 127;
begin
int1 := conv_integer(c);
int2 := conv_integer(d);
case current_s is
when s0=>
remainder <= 0;
done<='0';
int1:=int1-int2;
if(int1 < int2) then
remainder <= int1;
done<='1';
else
next_s <= s0;
end if;
end case;
end process;
end Behavioral;