entity long is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
done: out std_logic;
d : in std_logic_vector(5 downto 0);
c : in std_logic_vector(5 downto 0);
remainder : out std_logic_vector(5 downto 0));
end long;
architecture Behavioral of long is
type state_type is (s0,s1,s2);
signal current_s: state_type;
signal next_s: state_type;
signal int1:std_logic_vector(5 downto 0);
signal int2:std_logic_vector(5 downto 0);
signal result:std_logic_vector(5 downto 0);
begin
process (Clk, reset,c,d,current_s)
BEGIN
IF Clk'EVENT AND Clk='1' THEN
case current_s is
when s0=>
int1<=c;
int2<=d;
result<="000000";
current_s<=s1;
when s1=>
if(int1>"000000") then
result<=result(4 downto 0) & '0';
if(int1<=int2) then
int2<=int2-int1;
result<=result+1;
end if;
int1<='0' & int1(5 downto 1);
else
remainder<=int1;
current_s<=s2;
end if;
when s2=>
done<='1';
end case;
end if;
end process;
end Behavioral;