Modulation problem help!!

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mahesh690

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Hi,
I am designing a Transmitter using verilog,I want to synthesize the design to FPGA and then get the modulated bits through the MGT(Multi Gigabit Transmitter),my problem is since modulation formats like QPSK have negative constellation points they take more bits than positive constellation points.Any idea how to get around this.

Thanks,
Mahesh
 

I dont understand you: "negative constellation points imply more bits than possitive constellation"? Why?
 

I meant negative numbers take more bits to represent than positive bits(in Verilog)
 

Maybe you can represent the symbols with both possitive amplitude and phase, instead of real and imaginary parts which can be either possitive or negative.
 

I don't think you can represent what you said in verilog ,as far as i know,maybe you can help me.
 

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