ksrinivasan
Member level 3
Friends
I have a verilog netlist. I need to modify the verilog netlist to add input, output and inout pads.
Consider the following example
......
module bidirectional_buffer_width(y, a, e, b);
input [7:0] a;
input e;
output [7:0] b;
inout [7:0] y;
......
I modify this as follows
-----
module bidirectional_buffer_width(y_?, a_IP, e_IP, b_OP);
input [7:0] a_IP;
input e_IP;
output [7:0] b_OP;
inout [7:0] y_?
-------
For the input and output pads i just add _IP and _OP
what should i do for inout ??
----
Thanks in advance
Srinivasan
I have a verilog netlist. I need to modify the verilog netlist to add input, output and inout pads.
Consider the following example
......
module bidirectional_buffer_width(y, a, e, b);
input [7:0] a;
input e;
output [7:0] b;
inout [7:0] y;
......
I modify this as follows
-----
module bidirectional_buffer_width(y_?, a_IP, e_IP, b_OP);
input [7:0] a_IP;
input e_IP;
output [7:0] b_OP;
inout [7:0] y_?
-------
For the input and output pads i just add _IP and _OP
what should i do for inout ??
----
Thanks in advance
Srinivasan