Modify this VHDL code as follows

[r4am]

Modify this VHDL code by adding a parameter that sets the number of
flip-flops in the counter.

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Code VHDL - [expand]
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LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
ENTITY upcount IS
PORT ( Clock, Resetn, E : IN STD LOGIC ;
Q : OUT STD LOGIC VECTOR (3 DOWNTO 0)) ;
END upcount ;
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD LOGIC VECTOR (3 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn  ’0’ THEN
Count < ”0000” ;
ELSIF (Clock’EVENT AND Clock  ’1’) THEN
IF E  ’1’ THEN
Count < Count + 1 ;
ELSE
Count < Count ;
END IF ;
END IF ;
END PROCESS ;
Q < Count ;
END Behavior ;

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[imbichie]

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Code VHDL - [expand]
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LIBRARY ieee ;
USE ieee.std logic 1164.all ;
USE ieee.std logic unsigned.all ;
ENTITY upcount IS
generic (FFN : integer := 4 );
PORT ( Clock, Resetn, E : IN STD LOGIC ;
Q : OUT STD LOGIC VECTOR (FFN-1 DOWNTO 0)) ;
END upcount ;
ARCHITECTURE Behavior OF upcount IS
SIGNAL Count : STD LOGIC VECTOR (FFN-1 DOWNTO 0) ;
BEGIN
PROCESS ( Clock, Resetn )
BEGIN
IF Resetn  ’0’ THEN
Count < (others => '0') ;
ELSIF (Clock’EVENT AND Clock  ’1’) THEN
IF E  ’1’ THEN
Count < Count + 1 ;
ELSE
Count < Count ;
END IF ;
END IF ;
END PROCESS ;
Q < Count ;
END Behavior ;

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By changing the FFN's value, the FF number can adjust

I think this will works, i haven't compiled it.

 

[TrickyDicky]

looks like imbichie did your homework for you. I hope he sent an invoice.