modelsim & tcl testbench

[rosaldorosa]

I'm trying to create testbench which creates sin(x) real value, then converts to std_logic_vector, then sends to VHDL input (in CLK interval)
Does anyone know how tcl scripts influence tested code.
I found do file somewhere on the WEB.


vcom -novopt ../vhdl/traffic.vhd ../vhdl/queue.vhd ../vhdl/tb_traffic.vhd
source intersection.tcl
draw_intersection
set_light_state green .traffic.i.ns_light
set_light_state green .traffic.i.ew_light
vmap work work
vsim -novopt tb_traffic
source lights.tcl
...........

I would like to do sth similar, like
vcom ....
source sinx.tcl
vsim ...
send_sin_STD_LOGIC_VECTOR_value_to_VHDL_input