ModelSim, Synplify ASIC & Virage gate library

[kcmurphy88]

I'm trying to use ModelSim 6.1a to do gate level sim for an ASIC design. The RTL sims just fine, and the synthesis has no errors and all warnings are understood.

I'm using Synplify ASIC 5.26 for synthesis. My design is to be implemented using a set of Virage libraries. I'm having a problem with REMOVAL lines in the SDF generating errors (SDF-3262) going back to ModelSim.

Apparently the Virage gate library's Verilog view contains $recovery, but no $removal statements, but the .lib file has tons of recovery AND removal conditions on asynch reset (which, strictly speaking, I don't use, but the Virage flops seem to come that way).

So, when ModelSim runs and tries to load the gate-level design, it gags on the SDF's REMOVAL lines that it cannot correlate back to the verilog view.

Now, is this just something that a later version of ModelSim would solve? Or am I just missing a step someplace? Or is it a problem in my Virage fileset? No doubt I'm supposed to be using DC....

 

[kcmurphy88]

To answer my own question, the Virage memory library I was using has a discrepancy between the verilog view and the synopsis view, where the $removal lines are not present in the verilog, but REMOVAL statements are present in the lib. This causes errors when backannotating the netlist with the SDF. Solution: turn timing checks off.