Modelsim simulation of opencore MSP430 testbench

[kyungmin1125]

Hello,

We are running a gate level simulation on Modelsim to simulate the testbench provided with the MSP430 code taken from Opencore. So, we complied the MSP430 code in Quartus, which compiles fine. We clicked gate-level simulation and there are 3 timing models ("slow"k "slow", "fast") and we are not sure which one we should use.

Also, when we open Modelsim and try running the testbench, we get an error about not having the stimulus.v file. Are we supposed to write our own code to provide inputs to the gates? Does anyone have any examples of it?

Thank you

 

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We clicked gate-level simulation and there are 3 timing models ("slow"k "slow", "fast") and we are not sure which one we should use.

Are these timing models supplied with the core? I ask this because they sound somewhat like ASIC process library models. To simulate a "gate-level" you should compile through place and route in Quartus (not just run synthesis). Then generate a structural netlist of the design, which will output both the netlist and the corresponding SDF timing file. The SDF in this case will have the timing that Quartus reports for all the LUT, switches, memory, buffers, and metal delays in the part. You should then run the netlist with both the min/max delays from the SDF.

Also, when we open Modelsim and try running the testbench, we get an error about not having the stimulus.v file. Are we supposed to write our own code to provide inputs to the gates? Does anyone have any examples of it?
Thank you

The developer probably forgot to put that file in the repository. Makes me wonder if you're treading in unknown waters here....better watch out for reefs/sharks/ice_bergs... ;-)