Modelsim has a large buffer for simulation file output, I've observed the file needs 10's of KB before it will automatically write out the buffer.
vhdl 2008 has a flush(file); procedure
verilog has a $flush(file); system task
Neither of these will help unless you use them every time you write data to the file.
One way to do this, so you don't have to force a flush before the simulation is ended (which is what is occurring here), will be to store the data to be written in an array. When the array has enough entries you run a task/procedure that then opens a file for appending and writes all the data out to the file. In this way you will always be guaranteed to have X number of data added to the file each time (or dropped if you stop before the last X are ready to be written) and you won't slow the simulation down as much as doing: open-file, write-data, close-file or open-file ... write-data, flush, write-data, flush ...